LD1H (scalar plus vector) -- A64

This instruction performs a gather load of unsigned halfwords to Active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign-extended or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

32-bit scaled offset
(FEAT_SVE)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let g : integer = UInt(Pg); let esize : integer{} = 32; let msize : integer{} = 16; let offs_size : integer{} = 32; let unsigned : boolean = TRUE; let offs_unsigned : boolean = xs == '0'; let scale : integer = 1;

32-bit unpacked scaled offset
(FEAT_SVE)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 16; let offs_size : integer{} = 32; let unsigned : boolean = TRUE; let offs_unsigned : boolean = xs == '0'; let scale : integer = 1;

32-bit unpacked unscaled offset
(FEAT_SVE)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 16; let offs_size : integer{} = 32; let unsigned : boolean = TRUE; let offs_unsigned : boolean = xs == '0'; let scale : integer = 0;

32-bit unscaled offset
(FEAT_SVE)

Decode for this encoding

64-bit scaled offset
(FEAT_SVE)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 16; let offs_size : integer{} = 64; let unsigned : boolean = TRUE; let offs_unsigned : boolean = TRUE; let scale : integer = 1;

64-bit unscaled offset
(FEAT_SVE)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 16; let offs_size : integer{} = 64; let unsigned : boolean = TRUE; let offs_unsigned : boolean = TRUE; let scale : integer = 0;

Assembler Symbols

<Zt>	Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Zm>	Is the name of the offset scalable vector register, encoded in the "Zm" field.

<mod>

Is the index extend and shift specifier, encoded in xs:

xs	<mod>
0	UXTW
1	SXTW

Operation

CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; var base : bits(64); let mask : bits(PL) = P{}(g); var offset : bits(VL); var result : bits(VL); var data : bits(msize); let mbytes : integer{} = msize DIV 8; let contiguous : boolean = FALSE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement{PL}(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); end; else if n == 31 then CheckSPAlignment(); end; base = if n == 31 then SP{64}() else X{64}(n); offset = Z{VL}(m); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let offselt : bits(offs_size) = offset[e*:esize][offs_size-1:0]; let off : integer = if offs_unsigned then UInt(offselt) else SInt(offselt); let addr : bits(64) = AddressAdd(base, off << scale, accdesc); data = Mem{msize}(addr, accdesc); result[e*:esize] = Extend{esize}(data, unsigned); else result[e*:esize] = Zeros{esize}; end; end; Z{VL}(t) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	1	0	0	1	xs	1	Zm					0	1	0	Pg			Rn					Zt
																	U	ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	1	0	0	1	xs	1	Zm					0	1	0	Pg			Rn					Zt
							opc										U	ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	1	0	0	1	xs	0	Zm					0	1	0	Pg			Rn					Zt
							msz										U	ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	1	0	0	1	xs	0	Zm					0	1	0	Pg			Rn					Zt
							opc										U	ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	1	0	0	1	1	1	Zm					1	1	0	Pg			Rn					Zt
							opc										U	ff