Gather load quadwords
This instruction performs a gather load of quadwords to Active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rm | 1 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Zn); let m : integer = UInt(Rm); let g : integer = UInt(Pg);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <Xm> |
Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; CheckNonStreamingSVEEnabled(); let elements : integer = VL DIV 128; let mask : bits(PL) = P{}(g); var base : bits(VL); var offset : bits(64); var result : bits(VL); let contiguous : boolean = FALSE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if AnyActiveElement{PL}(mask, 128) then base = Z{VL}(n); offset = X{64}(m); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, 128) then let baddr : bits(64) = base[(2*e)*:64]; let addr : bits(64) = AddressAdd(baddr, offset, accdesc); result[e*:128] = Mem{128}(addr, accdesc); else result[e*:128] = Zeros{128}; end; end; Z{VL}(t) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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