Contiguous load and replicate eight words (immediate index)
This instruction loads eight contiguous words to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 32 in the range -256 to +224 added to the base address.
Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero.
The resulting 256-bit vector is then replicated to fill the destination vector. The instruction requires that the Effective SVE vector length is at least 256 bits.
Only the first eight predicate elements are used and higher numbered predicate elements are ignored.
ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | imm4 | 0 | 0 | 1 | Pg | Rn | Zt | |||||||||||||
| msz | ssz | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_F64MM) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let g : integer = UInt(Pg); let esize : integer{} = 32; let offset : integer = SInt(imm4);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field. |
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; if VL < 256 then EndOfDecode(Decode_UNDEF); end; let elements : integer = 256 DIV esize; var base : bits(64); let mask : bits(PL) = P{}(g); // low bits only var addr : bits(64); var result : bits(256); let mbytes : integer{} = esize DIV 8; let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = n != 31; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement{PL}(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); end; else if n == 31 then CheckSPAlignment(); end; end; base = if n == 31 then SP{64}() else X{64}(n); addr = AddressAdd(base, offset * elements * mbytes, accdesc); for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then result[e*:esize] = Mem{esize}(addr, accdesc); else result[e*:esize] = Zeros{esize}; end; addr = AddressIncrement(addr, mbytes, accdesc); end; Z{VL}(t) = ZeroExtend{VL}(Replicate{VL}(result));
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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