Load and broadcast unsigned word to vector
This instruction loads a single unsigned word from a memory address generated by a 64-bit scalar base address plus an immediate offset that is a multiple of 4 in the range 0 to 252.
The loaded data is broadcast into all Active elements of the destination vector, setting the Inactive elements to zero. If all elements are inactive, then the instruction will not perform a read from Device memory or cause a data abort.
It has encodings from 2 classes: 32-bit element and 64-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | imm6 | 1 | 1 | 0 | Pg | Rn | Zt | |||||||||||||||
| dtypeh | dtypel | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let g : integer = UInt(Pg); let esize : integer{} = 32; let msize : integer{} = 32; let unsigned : boolean = TRUE; let offset : integer = UInt(imm6);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | imm6 | 1 | 1 | 1 | Pg | Rn | Zt | |||||||||||||||
| dtypeh | dtypel | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 32; let unsigned : boolean = TRUE; let offset : integer = UInt(imm6);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 252, defaulting to 0, encoded in the "imm6" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; var base : bits(64); let mask : bits(PL) = P{}(g); var result : bits(VL); var data : bits(msize); let mbytes : integer{} = msize DIV 8; let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = n != 31; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement{PL}(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); end; else if n == 31 then CheckSPAlignment(); end; base = if n == 31 then SP{64}() else X{64}(n); let addr : bits(64) = AddressAdd(base, offset * mbytes, accdesc); data = Mem{msize}(addr, accdesc); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then result[e*:esize] = Extend{esize}(data, unsigned); else result[e*:esize] = Zeros{esize}; end; end; Z{VL}(t) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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