Contiguous load signed bytes to vector (scalar index)
This instruction performs a contiguous load of signed bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index that is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
It has encodings from 3 classes: 16-bit element , 32-bit element and 64-bit element
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| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | != 11111 | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| dtype | Rm | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 16; let msize : integer{} = 8; let unsigned : boolean = FALSE;
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| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | != 11111 | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| dtype | Rm | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 32; let msize : integer{} = 8; let unsigned : boolean = FALSE;
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| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | != 11111 | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| dtype | Rm | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 8; let unsigned : boolean = FALSE;
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; var base : bits(64); let mask : bits(PL) = P{}(g); var result : bits(VL); var data : bits(msize); var offset : bits(64); var addr : bits(64); let mbytes : integer{} = msize DIV 8; let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement{PL}(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); end; else if n == 31 then CheckSPAlignment(); end; end; base = if n == 31 then SP{64}() else X{64}(n); offset = X{64}(m); addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then data = Mem{msize}(addr, accdesc); result[e*:esize] = Extend{esize}(data, unsigned); else result[e*:esize] = Zeros{esize}; end; addr = AddressIncrement(addr, mbytes, accdesc); end; Z{VL}(t) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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