LD2 (multiple structures)

Load multiple 2-element structures to two registers

This instruction loads multiple 2-element structures from memory and writes the result to the two SIMD&FP registers, with de-interleaving.

For an example of de-interleaving, see LD3 (multiple structures).

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: No offset and Post-index

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	0	0	1	1	0	0	0	1	0	0	0	0	0	0	1	0	0	0	size		Rn					Rt
									L							opcode

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Rt); let n : integer = UInt(Rn); let m : integer = ARBITRARY : integer; let wback : boolean = FALSE; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31;

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	0	0	1	1	0	0	1	1	0	Rm					1	0	0	0	size		Rn					Rt
									L							opcode

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Rt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let wback : boolean = TRUE; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31;

size

<T>

16B

RESERVED

<imm>

#16

#32

Shared Decode

let datasize : integer{} = 64 << UInt(Q); let esize : integer{} = 8 << UInt(size); let elements : integer = datasize DIV esize; let rpt : integer = 1; let selem : integer = 2; // .1D format only permitted with LD1 & ST1 if size::Q == '110' && selem != 1 then EndOfDecode(Decode_UNDEF); end;

Operation

AArch64_CheckFPAdvSIMDEnabled(); var address : bits(64); var eaddr : bits(64); var rval : bits(datasize); var tt : integer; var offs : bits(64) = Zeros{64}; let ebytes : integer{} = esize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; for r = 0 to rpt-1 do for e = 0 to elements-1 do tt = (t + r) MOD 32; for s = 0 to selem-1 do rval = V{datasize}(tt); eaddr = AddressIncrement(address, offs, accdesc); rval[e*:esize] = Mem{esize}(eaddr, accdesc); V{datasize}(tt) = rval; offs = offs + ebytes; tt = (tt + 1) MOD 32; end; end; end; if wback then if m != 31 then offs = X{64}(m); end; address = AddressAdd(address, offs, accdesc); if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11