Contiguous load two-doubleword structures to two vectors (scalar index)
This instruction performs a contiguous load of two-doubleword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and a 64-bit scalar index register scaled by the element size (LSL option) and added to the base address. After each structure access the index value is incremented by two. The index register is not updated by the instruction.
Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive doublewords in memory that make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | != 11111 | 1 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| msz | opc | Rm | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 64; let nreg : integer{} = 2;
| <Zt1> |
Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. |
| <Zt2> |
Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; var base : bits(64); let mask : bits(PL) = P{}(g); var offset : bits(64); var addr : bits(64); let mbytes : integer{} = esize DIV 8; var values : array [[2]] of bits(VL); let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement{PL}(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); end; else if n == 31 then CheckSPAlignment(); end; end; base = if n == 31 then SP{64}() else X{64}(n); offset = X{64}(m); addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); for e = 0 to elements-1 do for r = 0 to nreg-1 do if ActivePredicateElement{PL}(mask, e, esize) then values[[r]][e*:esize] = Mem{esize}(addr, accdesc); else values[[r]][e*:esize] = Zeros{esize}; end; addr = AddressIncrement(addr, mbytes, accdesc); end; end; for r = 0 to nreg-1 do Z{VL}((t+r) MOD 32) = values[[r]]; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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