Contiguous load two-quadword structures to two vectors (immediate index)
This instruction performs a contiguous load of two-quadword structures, each to the same element number in two vector registers from the memory address generated by a 64-bit scalar base and an immediate index that is a multiple of 2 in the range -16 to 14 that is multiplied by the vector's in-memory size, irrespective of predication.
Each predicate element applies to the same element number in each of the two vector registers, or equivalently to the two consecutive quadwords in memory that make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the two destination vector registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | imm4 | 1 | 1 | 1 | Pg | Rn | Zt | |||||||||||||
| num | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let g : integer = UInt(Pg); let esize : integer{} = 128; let offset : integer = SInt(imm4); let nreg : integer{} = 2;
| <Zt1> |
Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. |
| <Zt2> |
Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; var base : bits(64); let mask : bits(PL) = P{}(g); var addr : bits(64); let mbytes : integer{} = esize DIV 8; var values : array [[2]] of bits(VL); let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = n != 31; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement{PL}(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); end; else if n == 31 then CheckSPAlignment(); end; end; base = if n == 31 then SP{64}() else X{64}(n); addr = AddressAdd(base, offset * elements * nreg * mbytes, accdesc); for e = 0 to elements-1 do for r = 0 to nreg-1 do if ActivePredicateElement{PL}(mask, e, esize) then values[[r]][e*:esize] = Mem{esize}(addr, accdesc); else values[[r]][e*:esize] = Zeros{esize}; end; addr = AddressIncrement(addr, mbytes, accdesc); end; end; for r = 0 to nreg-1 do Z{VL}((t+r) MOD 32) = values[[r]]; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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