LD3R

Load single 3-element structure and replicate to all lanes of three registers

This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: No offset and Post-index

No offset
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q001101010000001110sizeRnRt
LRo2opcodeS

Encoding

LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; var t : integer = UInt(Rt); let n : integer = UInt(Rn); let m : integer = ARBITRARY : integer; let wback : boolean = FALSE; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31;

Post-index
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q001101110Rm1110sizeRnRt
LRopcodeS

Encoding for the Immediate offset variant

Applies when (Rm == 11111)

LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>

Encoding for the Register offset variant

Applies when (Rm != 11111)

LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; var t : integer = UInt(Rt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let wback : boolean = TRUE; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31;

Assembler Symbols

<Vt>

Is the name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.

<T>

Is an arrangement specifier, encoded in (size :: Q):

size Q <T>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 0 1D
11 1 2D
<Vt2>

Is the name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.

<Vt3>

Is the name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the post-index immediate offset, encoded in size:

size <imm>
00 #3
01 #6
10 #12
11 #24
<Xm>

Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.

Shared Decode

var scale : bits(2) = opcode[2:1]; let selem : integer = UInt(opcode[0]::R) + 1; var replicate : boolean = FALSE; var index : integer; case scale of when '11' => // load and replicate if L == '0' || S == '1' then EndOfDecode(Decode_UNDEF); end; scale = size; replicate = TRUE; when '00' => index = UInt(Q::S::size); // B[0-15] when '01' => if size[0] == '1' then EndOfDecode(Decode_UNDEF); end; index = UInt(Q::S::size[1]); // H[0-7] when '10' => if size[1] == '1' then EndOfDecode(Decode_UNDEF); end; if size[0] == '0' then index = UInt(Q::S); // S[0-3] else if S == '1' then EndOfDecode(Decode_UNDEF); end; index = UInt(Q); // D[0-1] scale = '11'; end; end; let datasize : integer{} = 64 << UInt(Q); let esize : integer{} = 8 << UInt(scale);

Operation

AArch64_CheckFPAdvSIMDEnabled(); var address : bits(64); var eaddr : bits(64); var rval : bits(128); var element : bits(esize); var offs : bits(64) = Zeros{64}; let ebytes : integer{} = esize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if replicate then // load and replicate to all elements for s = 0 to selem-1 do eaddr = AddressIncrement(address, offs, accdesc); element = Mem{esize}(eaddr, accdesc); // replicate to fill 128- or 64-bit register V{datasize}(t) = Replicate{datasize}(element); offs = offs + ebytes; t = (t + 1) MOD 32; end; else // load/store one element per register for s = 0 to selem-1 do rval = V{128}(t); eaddr = AddressIncrement(address, offs, accdesc); rval[index*:esize] = Mem{esize}(eaddr, accdesc); V{128}(t) = rval; offs = offs + ebytes; t = ( t + 1 ) MOD 32; end; end; if wback then if m != 31 then offs = X{64}(m); end; address = AddressAdd(address, offs, accdesc); if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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