LD4W (scalar plus scalar)

Contiguous load four-word structures to four vectors (scalar index)

This instruction performs a contiguous load of four-word structures, each to the same element number in four vector registers from the memory address generated by a 64-bit scalar base and a 64-bit scalar index register scaled by the element size (LSL option) and added to the base address. After each structure access the index value is incremented by four. The index register is not updated by the instruction.

Each predicate element applies to the same element number in each of the four vector registers, or equivalently to the four consecutive words in memory that make up each structure. Inactive elements will not cause a read from Device memory or signal a fault, and the corresponding element is set to zero in each of the four destination vector registers.

SVE
(FEAT_SVE || FEAT_SME)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 32; let nreg : integer{} = 4;