Load-acquire exclusive pair of registers
This instruction derives an address from a base register value, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores.
If the destination registers are not both WZR or not both XZR, LDAXP loads from memory with Acquire semantics.
For more information about memory ordering semantics, see Load-Acquire, Load-AcquirePC, and Store-Release.
For information about addressing modes, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | sz | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | (1) | (1) | (1) | (1) | (1) | 1 | Rt2 | Rn | Rt | ||||||||||||
| L | Rs | o0 | |||||||||||||||||||||||||||||
let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let elsize : integer{} = 32 << UInt(sz); let datasize : integer{} = elsize * 2; let acqrel : boolean = TRUE; let tagchecked : boolean = n != 31; var rt_unknown : boolean = FALSE; if t == t2 then let c : Constraint = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN => rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDAXP.
| <Wt1> |
Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Wt2> |
Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
var address : bits(64); var data : bits(datasize); let dbytes : integer{} = datasize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let ispair : boolean = elsize == 64; // When elsize is 32, the access is single-copy atomic let accdesc : AccessDescriptor = CreateAccDescExLDST(MemOp_LOAD, acqrel, tagchecked, privileged, ispair, t, t2); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; AArch64_SetExclusiveMonitors(address, dbytes, accdesc); data = Mem{datasize}(address, accdesc); if rt_unknown then // ConstrainedUNPREDICTABLE case X{datasize}(t) = ARBITRARY : bits(datasize); // In this case t = t2 elsif BigEndian(accdesc.acctype) then X{elsize}(t) = data[elsize +: elsize]; X{elsize}(t2) = data[0 +: elsize]; else X{elsize}(t) = data[0 +: elsize]; X{elsize}(t2) = data[elsize +: elsize]; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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