Contiguous load first-fault unsigned bytes to vector (scalar index)
This instruction performs a contiguous load with first-faulting behavior of unsigned bytes to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index that is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 4 classes: 8-bit element , 16-bit element , 32-bit element and 64-bit element
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| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rm | 0 | 1 | 1 | Pg | Rn | Zt | ||||||||||||||
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if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 8; let msize : integer{} = 8; let unsigned : boolean = TRUE;
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| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Rm | 0 | 1 | 1 | Pg | Rn | Zt | ||||||||||||||
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if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 16; let msize : integer{} = 8; let unsigned : boolean = TRUE;
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| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | Rm | 0 | 1 | 1 | Pg | Rn | Zt | ||||||||||||||
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if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 32; let msize : integer{} = 8; let unsigned : boolean = TRUE;
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| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Rm | 0 | 1 | 1 | Pg | Rn | Zt | ||||||||||||||
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if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 8; let unsigned : boolean = TRUE;
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; var base : bits(64); let mask : bits(PL) = P{}(g); var result : bits(VL); let orig : bits(VL) = Z{}(t); var data : bits(msize); var offset : bits(64); var addr : bits(64); let mbytes : integer{} = msize DIV 8; var fault : boolean = FALSE; var faulted : boolean = FALSE; var unknown : boolean = FALSE; let contiguous : boolean = TRUE; let tagchecked : boolean = TRUE; var accdesc : AccessDescriptor = CreateAccDescSVEFF(contiguous, tagchecked); if !AnyActiveElement{PL}(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); end; else if n == 31 then CheckSPAlignment(); end; end; base = if n == 31 then SP{64}() else X{64}(n); offset = X{64}(m); addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); assert accdesc.first; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then if accdesc.first then // Mem[] will not return if a fault is detected for the First active element data = Mem{msize}(addr, accdesc); accdesc.first = FALSE; else // MemNF[] will return fault=TRUE if access is not performed for any reason (data, fault) = MemNF{msize}(addr, accdesc); faulted = faulted || ConstrainUnpredictableBool(Unpredictable_NONFAULT); end; else (data, fault) = (Zeros{msize}, FALSE); end; addr = AddressIncrement(addr, mbytes, accdesc); // FFR elements set to FALSE following a suppressed access/fault faulted = faulted || fault; if faulted then ElemFFR(e, esize) = '0'; end; // Value becomes CONSTRAINED UNPREDICTABLE after an FFR element is FALSE unknown = unknown || ElemFFR(e, esize) == '0'; if unknown then if !fault && ConstrainUnpredictableBool(Unpredictable_SVELDNFDATA) then result[e*:esize] = Extend{esize}(data, unsigned); elsif ConstrainUnpredictableBool(Unpredictable_SVELDNFZERO) then result[e*:esize] = Zeros{esize}; else // merge result[e*:esize] = orig[e*:esize]; end; else result[e*:esize] = Extend{esize}(data, unsigned); end; end; Z{VL}(t) = result;
2026-03_rel 2026-03-26 20:48:11
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