Gather load first-fault signed halfwords to vector (immediate index)
This instruction performs a gather load with first-faulting behavior of signed halfwords to Active elements of a vector register from memory addresses generated by a vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 2 classes: 32-bit element and 64-bit element
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| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | imm5 | 1 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
| msz | U | ff | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Zn); let g : integer = UInt(Pg); let esize : integer{} = 32; let msize : integer{} = 16; let unsigned : boolean = FALSE; let offset : integer = UInt(imm5);
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| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | imm5 | 1 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
| msz | U | ff | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Zn); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 16; let unsigned : boolean = FALSE; let offset : integer = UInt(imm5);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field. |
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); var base : bits(VL); var result : bits(VL); let orig : bits(VL) = Z{}(t); var data : bits(msize); let mbytes : integer{} = msize DIV 8; var fault : boolean = FALSE; var faulted : boolean = FALSE; var unknown : boolean = FALSE; let contiguous : boolean = FALSE; let tagchecked : boolean = TRUE; var accdesc : AccessDescriptor = CreateAccDescSVEFF(contiguous, tagchecked); if AnyActiveElement{PL}(mask, esize) then base = Z{VL}(n); end; assert accdesc.first; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let baddr : bits(64) = ZeroExtend{}(base[e*:esize]); let addr : bits(64) = AddressAdd(baddr, offset * mbytes, accdesc); if accdesc.first then // Mem[] will not return if a fault is detected for the First active element data = Mem{msize}(addr, accdesc); accdesc.first = FALSE; else // MemNF[] will return fault=TRUE if access is not performed for any reason (data, fault) = MemNF{msize}(addr, accdesc); faulted = faulted || ConstrainUnpredictableBool(Unpredictable_NONFAULT); end; else (data, fault) = (Zeros{msize}, FALSE); end; // FFR elements set to FALSE following a suppressed access/fault faulted = faulted || fault; if faulted then ElemFFR(e, esize) = '0'; end; // Value becomes CONSTRAINED UNPREDICTABLE after an FFR element is FALSE unknown = unknown || ElemFFR(e, esize) == '0'; if unknown then if !fault && ConstrainUnpredictableBool(Unpredictable_SVELDNFDATA) then result[e*:esize] = Extend{esize}(data, unsigned); elsif ConstrainUnpredictableBool(Unpredictable_SVELDNFZERO) then result[e*:esize] = Zeros{esize}; else // merge result[e*:esize] = orig[e*:esize]; end; else result[e*:esize] = Extend{esize}(data, unsigned); end; end; Z{VL}(t) = result;
2026-03_rel 2026-03-26 20:48:11
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