Load tag multiple
This instruction reads a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and writes the Allocation Tag read from address A to the destination register at 4*A<7:4>+3:4*A<7:4>. Bits of the destination register not written with an Allocation Tag are set to 0.
This instruction is UNDEFINED at EL0.
This instruction generates an Unchecked access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rt | ||||||||
| opc | imm9 | op2 | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_MTE2) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn);
| <Xt> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
if PSTATE.EL == EL0 then Undefined(); end; var data : bits(64) = Zeros{}; var address : bits(64); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let size : integer{} = 4 * (2 ^ (UInt(GMID_EL1().BS))); address = AlignDownSize(address, size); let count : integer = size >> LOG2_TAG_GRANULE; var index : integer = UInt(address[LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE]); let stzgm : boolean = FALSE; let accdesc : AccessDescriptor = CreateAccDescLDGSTG(MemOp_LOAD, stzgm, t); for i = 0 to count-1 do let tag : bits(4) = AArch64_MemTag(address, accdesc); data[index*:4] = tag; address = AddressIncrement(address, TAG_GRANULE, accdesc); index = index + 1; end; X{64}(t) = data;
2026-03_rel 2026-03-26 20:48:11
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