Load pair of SIMD&FP registers, with non-temporal hint
This instruction loads a pair of SIMD&FP registers from memory, issuing a hint to the memory system that the access is non-temporal. The address that is used for the load is calculated from a base register value and an optional immediate offset.
For information about non-temporal pair instructions, see Load/Store SIMD and Floating-point non-temporal pair.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
// Empty.
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDNP (SIMD&FP).
| <St1> |
Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <St2> |
Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Dt1> |
Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Dt2> |
Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Qt1> |
Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Qt2> |
Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let nontemporal : boolean = TRUE; let scale : integer{} = 2 + (UInt(opc) as integer{0..2}); let datasize : integer{} = 8 << scale; let offset : bits(64) = LSL(SignExtend{64}(imm7), scale); let tagchecked : boolean = n != 31; var rt_unknown : boolean = FALSE; if t == t2 then let c : Constraint = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN => rt_unknown = TRUE; // Result is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;
AArch64_CheckFPEnabled(); var address : bits(64); let dbytes : integer{} = datasize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let ispair : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged, ispair); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; address = AddressAdd(address, offset, accdesc); let data : bits(2*datasize) = Mem{2*datasize}(address, accdesc); if rt_unknown then V{datasize}(t) = ARBITRARY : bits(datasize); elsif BigEndian(accdesc.acctype) then V{datasize}(t2) = data[(datasize-1):0]; V{datasize}(t) = data[(2*datasize-1):datasize]; else V{datasize}(t) = data[(datasize-1):0]; V{datasize}(t2) = data[(2*datasize-1):datasize]; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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