LDNT1H (vector plus scalar)

Gather load non-temporal unsigned halfwords

This instruction performs a non-temporal gather load of unsigned halfwords to Active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.

A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 2 classes: 32-bit unscaled offset and 64-bit unscaled offset

32-bit unscaled offset
(FEAT_SVE2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Zn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 32; let msize : integer{} = 16; let unsigned : boolean = TRUE;

64-bit unscaled offset
(FEAT_SVE2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Zn); let m : integer = UInt(Rm); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 16; let unsigned : boolean = TRUE;