Load register (immediate)
This instruction loads a word or doubleword from memory and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes. The Unsigned offset variant scales the immediate offset value by the size of the value accessed before adding it to the base register value.
It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset
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| 1 | x | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | imm9 | 0 | 1 | Rn | Rt | ||||||||||||||||
| size | VR | opc | |||||||||||||||||||||||||||||
var wback : boolean = TRUE; let postindex : boolean = TRUE; let scale : integer{} = UInt(size); let offset : bits(64) = SignExtend{}(imm9);
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| 1 | x | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | imm9 | 1 | 1 | Rn | Rt | ||||||||||||||||
| size | VR | opc | |||||||||||||||||||||||||||||
var wback : boolean = TRUE; let postindex : boolean = FALSE; let scale : integer{} = UInt(size); let offset : bits(64) = SignExtend{}(imm9);
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| 1 | x | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | imm12 | Rn | Rt | |||||||||||||||||||
| size | VR | opc | |||||||||||||||||||||||||||||
var wback : boolean = FALSE; let postindex : boolean = FALSE; let scale : integer{} = UInt(size); let offset : bits(64) = LSL(ZeroExtend{64}(imm12), scale);
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDR (immediate).
| <Wt> |
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <simm> |
Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field. |
| <Xt> |
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let datasize : integer{} = 8 << scale; let regsize : integer{} = if datasize == 64 then 64 else 32; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31; var c : Constraint; var wb_unknown : boolean = FALSE; if wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS => wback = FALSE; // Writeback is suppressed when Constraint_UNKNOWN => wb_unknown = TRUE; // Writeback is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;
var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if !postindex then address = AddressAdd(address, offset, accdesc); end; let data : bits(datasize) = Mem{datasize}(address, accdesc); X{regsize}(t) = ZeroExtend{regsize}(data); if wback then if wb_unknown then address = ARBITRARY : bits(64); elsif postindex then address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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