LDR (literal, SIMD&FP) -- A64

This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from the PC value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Literal
(FEAT_FP)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); if opc == '11' then EndOfDecode(Decode_UNDEF); end; let size : integer{} = 4 << (UInt(opc) as integer{0..2}); let nontemporal : boolean = FALSE; let tagchecked : boolean = FALSE; let offset : bits(64) = SignExtend{}(imm19::'00');

Assembler Symbols

<St>	Is the 32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

<label>

Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

<Dt>	Is the 64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

<Qt>	Is the 128-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

Operation

let address : bits(64) = PC64() + offset; AArch64_CheckFPEnabled(); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); let data : bits(size*8) = Mem{size*8}(address, accdesc); V{size*8}(t) = data;

2026-03_rel 2026-03-26 20:48:11

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opc		0	1	1	1	0	0	imm19																			Rt
					VR