Load predicate register
This instruction loads a predicate register from a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 that is multiplied by the current predicate register size in bytes. This instruction is unpredicated.
The load is performed as contiguous byte accesses, each containing 8 consecutive predicate bits in ascending element order, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then a general-purpose base register must be aligned to 2 bytes.
For programmer convenience, an assembler must also accept a predicate-as-counter register name for the destination predicate register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | imm9h | 0 | 0 | 0 | imm9l | Rn | 0 | Pt | ||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Pt); let n : integer = UInt(Rn); let imm : integer = SInt(imm9h::imm9l);
| <Pt> |
Is the name of the destination scalable predicate register, encoded in the "Pt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = PL DIV 8; var base : bits(64); let offset : integer = imm * elements; var result : bits(PL); let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let predicated : boolean = FALSE; let tagchecked : boolean = n != 31; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, predicated, tagchecked); if n == 31 then CheckSPAlignment(); base = SP{64}(); else base = X{64}(n); end; var addr : bits(64) = AddressAdd(base, offset, accdesc); let aligned : boolean = IsAlignedSize(base, 2); if !aligned && AlignmentEnforced() then let fault : FaultRecord = AlignmentFault(accdesc, addr); AArch64_Abort(fault); end; for e = 0 to elements-1 do result[e*:8] = AArch64_MemSingle{8}(addr, accdesc, aligned); addr = AddressIncrement(addr, 1, accdesc); end; P{PL}(t) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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