LDR (register, SIMD&FP) -- A64

This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

SIMD&FP registers
(FEAT_FP)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if option[1] == '0' then EndOfDecode(Decode_UNDEF); end; // sub-word index if opc[1] == '1' && size != '00' then EndOfDecode(Decode_UNDEF); end; let scale : integer{} = if opc[1] == '1' then 4 else UInt(size); let extend_type : ExtendType = DecodeRegExtend(option); let shift : integer{} = if S == '1' then scale else 0;

Assembler Symbols

<Bt>	Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Wm>	When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.

<Xm>	When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.

For the "8-bit with extended register offset" variant: is the index extend specifier, encoded in option:

option	<extend>
010	UXTW
110	SXTW
111	SXTX

For the "128-bit", "16-bit", "32-bit", and "64-bit" variants: is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted, encoded in option:

option	<extend>
010	UXTW
011	LSL
110	SXTW
111	SXTX

For the "8-bit with extended register offset" and "8-bit with shifted register offset" variants: is the index shift amount, it must be #0, encoded in "S" as 0 if omitted, or as 1 if present.

For the "16-bit" variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:

S	<amount>
0	#0
1	#1

For the "32-bit" variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:

S	<amount>
0	#0
1	#2

For the "64-bit" variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:

S	<amount>
0	#0
1	#3

For the "128-bit" variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:

S	<amount>
0	#0
1	#4

<Ht>	Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<St>	Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt>	Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt>	Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

Shared Decode

let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let datasize : integer{} = 8 << scale; let nontemporal : boolean = FALSE; let tagchecked : boolean = TRUE;

Operation

AArch64_CheckFPEnabled(); let offset : bits(64) = ExtendReg{}(m, extend_type, shift); var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; address = AddressAdd(address, offset, accdesc); V{datasize}(t) = Mem{datasize}(address, accdesc);

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
size		1	1	1	1	0	0	x	1	1	Rm					option			S	1	0	Rn					Rt
					VR			opc