LDRB (immediate)

Load register byte (immediate)

This instruction loads a byte from memory, zero-extends it, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.

It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset

Post-index

313029282726252423222120191817161514131211109876543210
00111000010imm901RnRt
sizeVRopc

Encoding

LDRB <Wt>, [<Xn|SP>], #<simm>

Decode for this encoding

var wback : boolean = TRUE; let postindex : boolean = TRUE; let offset : bits(64) = SignExtend{}(imm9);

Pre-index

313029282726252423222120191817161514131211109876543210
00111000010imm911RnRt
sizeVRopc

Encoding

LDRB <Wt>, [<Xn|SP>, #<simm>]!

Decode for this encoding

var wback : boolean = TRUE; let postindex : boolean = FALSE; let offset : bits(64) = SignExtend{}(imm9);

Unsigned offset

313029282726252423222120191817161514131211109876543210
0011100101imm12RnRt
sizeVRopc

Encoding

LDRB <Wt>, [<Xn|SP>{, #<pimm>}]

Decode for this encoding

var wback : boolean = FALSE; let postindex : boolean = FALSE; let offset : bits(64) = LSL(ZeroExtend{64}(imm12), 0);

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRH (immediate).

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<pimm>

Is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

Shared Decode

let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31; var c : Constraint; var wb_unknown : boolean = FALSE; if wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS => wback = FALSE; // Writeback is suppressed when Constraint_UNKNOWN => wb_unknown = TRUE; // Writeback is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;

Operation

var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if !postindex then address = AddressAdd(address, offset, accdesc); end; let data : bits(8) = Mem{8}(address, accdesc); X{32}(t) = ZeroExtend{32}(data); if wback then if wb_unknown then address = ARBITRARY : bits(64); elsif postindex then address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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