Atomic bit set on quadword
This instruction atomically loads a 128-bit quadword from memory, performs a bitwise OR with the value held in a pair of registers on it, and stores the result back to memory. The value initially loaded from memory is returned in the same pair of registers.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | A | R | 1 | Rt2 | 0 | 0 | 1 | 1 | 0 | 0 | Rn | Rt | ||||||||||||
| S | o3 | opc | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSE128) then EndOfDecode(Decode_UNDEF); end; if Rt == '11111' then EndOfDecode(Decode_UNDEF); end; if Rt2 == '11111' then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let acquire : boolean = A == '1'; let release : boolean = R == '1'; let tagchecked : boolean = n != 31; var rt_unknown : boolean = FALSE; if t == t2 then let c : Constraint = ConstrainUnpredictable(Unpredictable_LSE128OVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN => rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly 128-bit Atomic Memory Operations.
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
var address : bits(64); let value1 : bits(64) = X{}(t); let value2 : bits(64) = X{}(t2); var data : bits(128); var store_value : bits(128); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_ORR, acquire, release, tagchecked, privileged, t, t2, t, t2); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; store_value = if BigEndian(accdesc.acctype) then value1::value2 else value2::value1; let comparevalue : bits(128) = ARBITRARY : bits(128); // Irrelevant when not executing CAS data = MemAtomic{128}(address, comparevalue, store_value, accdesc); if rt_unknown then data = ARBITRARY : bits(128); end; if BigEndian(accdesc.acctype) then X{64}(t) = data[127:64]; X{64}(t2) = data[63:0]; else X{64}(t) = data[63:0]; X{64}(t2) = data[127:64]; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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