LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB

Atomic unsigned minimum on byte

This instruction atomically loads an 8-bit byte from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

This instruction is used by the alias STUMINB, STUMINLB.

Integer
(FEAT_LSE)

313029282726252423222120191817161514131211109876543210
00111000AR1Rs011100RnRt
sizeVRo3opc

Encoding for the No memory ordering variant

Applies when (A == 0 && R == 0)

LDUMINB <Ws>, <Wt>, [<Xn|SP>]

Encoding for the Acquire variant

Applies when (A == 1 && R == 0)

LDUMINAB <Ws>, <Wt>, [<Xn|SP>]

Encoding for the Acquire-release variant

Applies when (A == 1 && R == 1)

LDUMINALB <Ws>, <Wt>, [<Xn|SP>]

Encoding for the Release variant

Applies when (A == 0 && R == 1)

LDUMINLB <Ws>, <Wt>, [<Xn|SP>]

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LSE) then EndOfDecode(Decode_UNDEF); end; let s : integer{} = UInt(Rs); let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let acquire : boolean = A == '1' && Rt != '11111'; let release : boolean = R == '1'; let tagchecked : boolean = n != 31;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Alias Conditions

AliasIs preferred when
STUMINB, STUMINLBA == '0' && Rt == '11111'

Operation

var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_UMIN, acquire, release, tagchecked, privileged, t, s); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let comparevalue : bits(8) = ARBITRARY : bits(8); // Irrelevant when not executing CAS let value : bits(8) = X{8}(s); let data : bits(8) = MemAtomic{}(address, comparevalue, value, accdesc); if t != 31 then X{32}(t) = ZeroExtend{32}(data); end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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