LSR (immediate, unpredicated) -- A64

This instruction shifts right by immediate, inserting zeroes, each element of the source vector, and places the results in the corresponding elements of the destination vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

SVE
(FEAT_SVE || FEAT_SME)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let tsize : bits(4) = tszh::tszl; if tsize == '0000' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << HighestSetBitNZ(tsize); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let shift : integer = (2 * esize) - UInt(tsize::imm3);

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in (tszh :: tszl):

tszh	tszl	<T>
00	00	RESERVED
00	01	B
00	1x	H
01	xx	S
1x	xx	D

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand1 : bits(VL) = Z{}(n); var result : bits(VL); for e = 0 to elements-1 do let element1 : bits(esize) = operand1[e*:esize]; result[e*:esize] = LSR(element1, shift); end; Z{VL}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11

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0	0	0	0	0	1	0	0	tszh		1	tszl		imm3			1	0	0	1	0	1	Zn					Zd
																					U