LUTI4 (four registers, 8-bit) -- A64

This instruction copies 8-bit elements from ZT0 to four destination vectors using packed 4-bit indices in the two source vectors.

Consecutive
(FEAT_SME_LUTv2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_LUTv2) then EndOfDecode(Decode_UNDEF); end; if size != '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let isize : integer{} = 4; let n : integer = UInt(Zn::'0'); let dstride : integer = 1; let d : integer = UInt(Zd::'00'); let nreg : integer{} = 4;

Strided
(FEAT_SME2p1 && FEAT_SME_LUTv2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2p1) || !IsFeatureImplemented(FEAT_SME_LUTv2) then EndOfDecode(Decode_UNDEF); end; if size != '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let isize : integer{} = 4; let n : integer = UInt(Zn::'0'); let dstride : integer = 4; let d : integer = UInt(D::'00'::Zd); let nreg : integer{} = 4;

Assembler Symbols

<Zd1>	For the "Consecutive" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.
	For the "Strided" variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 of the destination multi-vector group, encoded as "D:'00':Zd".

<Zd4>	For the "Consecutive" variant: is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.
	For the "Strided" variant: is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 of the destination multi-vector group, encoded as "D:'11':Zd".

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zd2>

Is the name of the second scalable vector register Z4-Z7 or Z20-Z23 of the destination multi-vector group, encoded as "D:'01':Zd".

<Zd3>

Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 of the destination multi-vector group, encoded as "D:'10':Zd".

Operation

CheckStreamingSVEEnabled(); CheckSMEZT0Enabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let indexes : bits(2*VL) = Z{VL}(n+1) :: Z{VL}(n+0); var dst : integer = d; let table : bits(512) = ZT0{}(); for r = 0 to nreg-1 do let base : integer = r * elements; var result : bits(VL); for e = 0 to elements-1 do let index : integer = UInt(indexes[(base+e)*:isize]); result[e*:esize] = table[index*:32][esize-1:0]; end; Z{VL}(dst) = result; dst = dst + dstride; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11