LUTI4 (8-bit and 16-bit) -- A64

This instruction copies indexed 8-bit or 16-bit elements from the low 128 or 256 bits of the table vector, or from the low 128 bits of the two table vectors to the destination vector using packed 4-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index. This instruction is unpredicated.

Byte, single register table
((FEAT_SVE2 || FEAT_SME2) && FEAT_LUT)

Decode for this encoding

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_LUT)) then EndOfDecode(Decode_UNDEF); end; let isize : integer{} = 4; let esize : integer{} = 8; let ntblr : integer = 1; let m : integer = UInt(Zm); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let part : integer = UInt(i1);

Halfword, two register table
((FEAT_SVE2 || FEAT_SME2) && FEAT_LUT)

Decode for this encoding

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_LUT)) then EndOfDecode(Decode_UNDEF); end; let isize : integer{} = 4; let esize : integer{} = 16; let ntblr : integer = 2; let m : integer = UInt(Zm); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let part : integer = UInt(i2);

Halfword, single register table
((FEAT_SVE2 || FEAT_SME2) && FEAT_LUT)

Decode for this encoding

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_LUT)) then EndOfDecode(Decode_UNDEF); end; if MaxImplementedAnyVL() < 256 then EndOfDecode(Decode_UNDEF); end; let isize : integer{} = 4; let esize : integer{} = 16; let ntblr : integer = 1; let m : integer = UInt(Zm); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let part : integer = UInt(i2);

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn>	Is the name of the table vector register, encoded in the "Zn" field.

<Zm>	Is the name of the source scalable vector register, encoded in the "Zm" field.

<index>	For the "Byte, single register table" variant: is the vector segment index, in the range 0 to 1, encoded in the "i1" field.
	For the "Halfword, single register table" and "Halfword, two register table" variants: is the vector segment index, in the range 0 to 3, encoded in the "i2" field.

<Zn1>

Is the name of the first table vector register, encoded as "Zn".

<Zn2>

Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32.

Operation

if IsFeatureImplemented(FEAT_SME2) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); if ntblr == 1 && esize == 16 && VL < 256 then EndOfDecode(Decode_UNDEF); end; let elements : integer = VL DIV esize; let tablesize : integer = if ntblr == 1 && esize == 16 then 256 else 128; let eltspertable : integer = tablesize DIV esize; let ibase : integer = elements * part; let indexes : bits(VL) = Z{}(m); let table1 : bits(VL) = Z{}(n+0); let table2 : bits(VL) = if ntblr == 2 then Z{VL}((n+1) MOD 32) else Zeros{VL}; var result : bits(VL); var res : bits(esize); for e = 0 to elements-1 do let index : integer = UInt(indexes[(ibase + e)*:isize]); if index < eltspertable then res = table1[index*:esize]; else assert ntblr == 2; res = table2[(index - eltspertable)*:esize]; end; result[e*:esize] = res; end; Z{VL}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	i1	1	1	Zm					1	0	1	0	0	1	Zn					Zd

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	i2		1	Zm					1	0	1	1	0	1	Zn					Zd
																				op

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	i2		1	Zm					1	0	1	1	1	1	Zn					Zd
																				op