MADPT

Multiply-add checked pointer vectors to multiplicand

This instruction multiplies, with overflow check, the elements of the first and second source vectors and adds the results of multiplication, with pointer check, to elements of the third (addend) vector. The final results are destructively placed in the destination and first source (multiplicand) vector.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

SVE2
(FEAT_SVE && FEAT_CPA)

313029282726252423222120191817161514131211109876543210
01000100110Zm110110ZaZdn
opco2

Encoding

MADPT <Zdn>.D, <Zm>.D, <Za>.D

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_CPA) then EndOfDecode(Decode_UNDEF); end; let dn : integer = UInt(Zdn); let m : integer = UInt(Zm); let a : integer = UInt(Za);

Assembler Symbols

<Zdn>

Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Za>

Is the name of the third source scalable vector register, encoded in the "Za" field.

Operation

CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 64; let operand1 : bits(VL) = Z{}(dn); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(a); var result : bits(VL); for e = 0 to elements-1 do let element1 : integer = SInt(operand1[e*:64]); let element2 : integer = SInt(operand2[e*:64]); let product : integer = element1 * element2; let overflow : boolean = (product != SInt(product[63:0])); let addend : bits(64) = operand3[e*:64]; result[e*:64] = PointerMultiplyAddCheck(addend + product, addend, overflow); end; Z{VL}(dn) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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