MLA (by element)

Multiply-add to accumulator (vector, by element)

This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vector
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q101111sizeLMRm0000H0RnRd
Uo2

Encoding

MLA <Vd>.<T>, <Vn>.<T>, V<m>.<Ts>[<index>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; var Rmhi : bit; case size of when '01' => index = UInt(H::L::M); Rmhi = '0'; when '10' => index = UInt(H::L); Rmhi = M; otherwise => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in (size :: Q):

size Q <T>
00 x RESERVED
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 x RESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<m>

Is the number of the second SIMD&FP source register, encoded in (size :: M :: Rm):

size <m>
00 RESERVED
01 UInt('0' :: Rm)
10 UInt(M :: Rm)
11 RESERVED
Restricted to 0-15 when element size <Ts> is H.
<Ts>

Is an element size specifier, encoded in size:

size <Ts>
00 RESERVED
01 H
10 S
11 RESERVED
<index>

Is the element index, encoded in (size :: H :: L :: M):

size <index>
00 RESERVED
01 UInt(H :: L :: M)
10 UInt(H :: L)
11 RESERVED

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(idxdsize) = V{}(m); let operand3 : bits(datasize) = V{}(d); var result : bits(datasize); var element1 : integer; var element2 : integer; var product : bits(esize); element2 = UInt(operand2[index*:esize]); for e = 0 to elements-1 do element1 = UInt(operand1[e*:esize]); product = (element1 * element2)[esize-1:0]; result[e*:esize] = operand3[e*:esize] + product; end; V{datasize}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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