Move immediate (vector)
This instruction places an immediate constant into every vector element of the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | op | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd | |||||||
| o2 | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let rd : integer = UInt(Rd); let datasize : integer{} = 64 << UInt(Q); let imm64 : bits(64) = AdvSIMDExpandImm(op, cmode, a::b::c::d::e::f::g::h); let imm : bits(datasize) = Replicate{}(imm64);
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <imm8> |
Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h". |
| <amount> |
For the "16-bit shifted immediate" variant: is the shift amount
encoded in
| ||||||||||
|
For the "32-bit shifted immediate" variant: is the shift amount
encoded in
| |||||||||||
|
For the "32-bit shifting ones" variant: is the shift amount
encoded in
|
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <imm> |
Is a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', encoded in "a:b:c:d:e:f:g:h". |
2026-03_rel 2026-03-26 20:48:11
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