Bitwise invert predicate
This instruction performs a bitwise invert of each active element of the source predicate, and places the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. This instruction does not set the condition flags.
This is an alias of EOR (predicates). This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Pm | 0 | 1 | Pg | 1 | Pn | 0 | Pd | ||||||||||||
| op | S | o2 | o3 | ||||||||||||||||||||||||||||
is equivalent to
EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pg>.B
and is the preferred disassembly when Pm == Pg.
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
| <Pn> |
Is the name of the source scalable predicate register, encoded in the "Pn" field. |
The description of EOR (predicates) gives the operational pseudocode for this instruction.
The description of EOR (predicates) gives the operational information for this instruction.
2026-03_rel 2026-03-26 20:48:11
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