Bitwise inclusive OR inverted predicate, setting the condition flags
This instruction performs a bitwise inclusive OR between the active elements of the first source predicate and the inverted corresponding elements of the second source predicate, and places the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. This instruction sets the First (N), None (Z), and !Last (C) condition flags based on the predicate result, and sets the V flag to zero.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | Pm | 0 | 1 | Pg | 0 | Pn | 1 | Pd | ||||||||||||
| op | S | o2 | o3 | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8; let g : integer = UInt(Pg); let n : integer = UInt(Pn); let m : integer = UInt(Pm); let d : integer = UInt(Pd); let setflags : boolean = TRUE;
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
| <Pn> |
Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
| <Pm> |
Is the name of the second source scalable predicate register, encoded in the "Pm" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand1 : bits(PL) = P{}(n); let operand2 : bits(PL) = P{}(m); var result : bits(PL); let psize : integer{} = esize DIV 8; for e = 0 to elements-1 do let element1 : bit = PredicateElement{PL}(operand1, e, esize); let element2 : bit = PredicateElement{PL}(operand2, e, esize); if ActivePredicateElement{PL}(mask, e, esize) then result[e*:psize] = ZeroExtend{psize}(element1 OR (NOT element2)); else result[e*:psize] = ZeroExtend{psize}('0'); end; end; if setflags then PSTATE.[N,Z,C,V] = PredTest{PL}(mask, result, esize); end; P{PL}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.
2026-03_rel 2026-03-26 20:48:11
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