Bitwise inclusive OR reduction to scalar
This instruction performs a bitwise inclusive OR between the elements of the source vector, and places the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as zero.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Pg | Zn | Vd | |||||||||||
| opc | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Vd);
| <V> |
Is a width specifier,
encoded in
|
| <d> |
Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <T> |
Is the size specifier,
encoded in
|
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(n) else Zeros{VL}; var result : bits(esize) = Zeros{esize}; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then result = result OR operand[e*:esize]; end; end; V{esize}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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