PNEXT

Find next active predicate

This instruction constructs a loop that iterates over all true elements in the vector select predicate register. If all elements in the first source predicate register are false it determines the first true element in the vector select predicate register, otherwise it determines the next true element in the vector select predicate register that follows the last true element in the first source predicate register. All elements of the destination predicate register are set to false, except the element corresponding to the determined vector select element, if any, which is set to true. This instruction sets the First (N), None (Z), and !Last (C) condition flags based on the predicate result, and sets the V flag to zero.

SVE
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00100101size0110011100010Pv0Pdn

Encoding

PNEXT <Pdn>.<T>, <Pv>, <Pdn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let v : integer = UInt(Pv); let dn : integer = UInt(Pdn);

Assembler Symbols

<Pdn>

Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Pv>

Is the name of the vector select predicate register, encoded in the "Pv" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer{} = VL DIV esize; let mask : bits(PL) = P{}(v); let operand : bits(PL) = P{}(dn); var result : bits(PL) = Zeros{PL}; let psize : integer{} = esize DIV 8; var next : integer = LastActiveElement{PL}(operand, esize) + 1; while next < elements && (!ActivePredicateElement{PL}(mask, next, esize)) looplimit elements do next = next + 1; end; if next < elements then result[next*:psize] = ZeroExtend{psize}('1'); end; PSTATE.[N,Z,C,V] = PredTest{PL}(mask, result, esize); P{PL}(dn) = result;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.


2026-03_rel 2026-03-26 20:48:11

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