Gather prefetch doublewords (vector plus immediate)
This instruction performs a gather prefetch of doublewords from the active memory addresses generated by a vector base plus immediate index. The index is a multiple of 8 in the range 0 to 248. Inactive addresses are not prefetched from memory.
The <prfop> operand specifies the prefetch hint as follows:
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 2 classes: 32-bit element and 64-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | imm5 | 1 | 1 | 1 | Pg | Zn | 0 | prfop | |||||||||||||
| msz | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let g : integer = UInt(Pg); let n : integer = UInt(Zn); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let scale : integer = 3; let offset : integer = UInt(imm5);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | imm5 | 1 | 1 | 1 | Pg | Zn | 0 | prfop | |||||||||||||
| msz | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let g : integer = UInt(Pg); let n : integer = UInt(Zn); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let scale : integer = 3; let offset : integer = UInt(imm5);
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field. |
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); var base : bits(VL); if AnyActiveElement{PL}(mask, esize) then base = Z{VL}(n); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let addr : bits(64) = ZeroExtend{64}(base[e*:esize]) + (offset << scale); Hint_Prefetch(addr, pref_hint, level, stream); end; end;
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.