Gather prefetch doublewords (scalar plus vector)
This instruction performs a gather prefetch of doublewords from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign-extended or zero-extended from 32 to 64 bits and then multiplied by 8. Inactive addresses are not prefetched from memory.
The <prfop> operand specifies the prefetch hint as follows:
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 3 classes: 32-bit scaled offset , 32-bit unpacked scaled offset and 64-bit scaled offset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | xs | 1 | Zm | 0 | 1 | 1 | Pg | Rn | 0 | prfop | |||||||||||||
| msz | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let g : integer = UInt(Pg); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let offs_size : integer{} = 32; let offs_unsigned : boolean = (xs == '0'); let scale : integer = 3;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | xs | 1 | Zm | 0 | 1 | 1 | Pg | Rn | 0 | prfop | |||||||||||||
| msz | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let g : integer = UInt(Pg); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let offs_size : integer{} = 32; let offs_unsigned : boolean = (xs == '0'); let scale : integer = 3;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 1 | 1 | 1 | Pg | Rn | 0 | prfop | |||||||||||||
| msz | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let g : integer = UInt(Pg); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let offs_size : integer{} = 64; let offs_unsigned : boolean = TRUE; let scale : integer = 3;
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Zm> |
Is the name of the offset scalable vector register, encoded in the "Zm" field. |
| <mod> |
Is the index extend and shift specifier,
encoded in
|
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); var base : bits(64); var offset : bits(VL); if AnyActiveElement{PL}(mask, esize) then base = if n == 31 then SP{64}() else X{64}(n); offset = Z{VL}(m); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let offselt : bits(offs_size) = offset[e*:esize][offs_size-1:0]; let off : integer = if offs_unsigned then UInt(offselt) else SInt(offselt); let addr : bits(64) = base + (off << scale); Hint_Prefetch(addr, pref_hint, level, stream); end; end;
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.