PRFW (vector plus immediate)

Gather prefetch words (vector plus immediate)

This instruction performs a gather prefetch of words from the active memory addresses generated by a vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive addresses are not prefetched from memory.

The <prfop> operand specifies the prefetch hint as follows:

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 2 classes: 32-bit element and 64-bit element

32-bit element
(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
10000101000imm5111PgZn0prfop
msz

Encoding

PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let g : integer = UInt(Pg); let n : integer = UInt(Zn); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let scale : integer = 2; let offset : integer = UInt(imm5);

64-bit element
(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11000101000imm5111PgZn0prfop
msz

Encoding

PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let g : integer = UInt(Pg); let n : integer = UInt(Zn); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let scale : integer = 2; let offset : integer = UInt(imm5);

Assembler Symbols

<prfop>

Is the prefetch operation specifier, encoded in prfop:

prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the base scalable vector register, encoded in the "Zn" field.

<imm>

Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

Operation

CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); var base : bits(VL); if AnyActiveElement{PL}(mask, esize) then base = Z{VL}(n); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let addr : bits(64) = ZeroExtend{64}(base[e*:esize]) + (offset << scale); Hint_Prefetch(addr, pref_hint, level, stream); end; end;


2026-03_rel 2026-03-26 20:48:11

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