PRFW (scalar plus vector)

Gather prefetch words (scalar plus vector)

This instruction performs a gather prefetch of words from the active memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign-extended or zero-extended from 32 to 64 bits and then multiplied by 4. Inactive addresses are not prefetched from memory.

The <prfop> operand specifies the prefetch hint as follows:

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 3 classes: 32-bit scaled offset , 32-bit unpacked scaled offset and 64-bit scaled offset

32-bit scaled offset
(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
100001000xs1Zm010PgRn0prfop
msz

Encoding

PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let g : integer = UInt(Pg); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let offs_size : integer{} = 32; let offs_unsigned : boolean = (xs == '0'); let scale : integer = 2;

32-bit unpacked scaled offset
(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
110001000xs1Zm010PgRn0prfop
msz

Encoding

PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let g : integer = UInt(Pg); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let offs_size : integer{} = 32; let offs_unsigned : boolean = (xs == '0'); let scale : integer = 2;

64-bit scaled offset
(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11000100011Zm110PgRn0prfop
msz

Encoding

PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let g : integer = UInt(Pg); let n : integer = UInt(Rn); let m : integer = UInt(Zm); let level : integer = UInt(prfop[2:1]); let stream : boolean = (prfop[0] == '1'); let pref_hint : PrefetchHint = if prfop[3] == '0' then Prefetch_READ else Prefetch_WRITE; let offs_size : integer{} = 64; let offs_unsigned : boolean = TRUE; let scale : integer = 2;

Assembler Symbols

<prfop>

Is the prefetch operation specifier, encoded in prfop:

prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Zm>

Is the name of the offset scalable vector register, encoded in the "Zm" field.

<mod>

Is the index extend and shift specifier, encoded in xs:

xs <mod>
0 UXTW
1 SXTW

Operation

CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); var base : bits(64); var offset : bits(VL); if AnyActiveElement{PL}(mask, esize) then base = if n == 31 then SP{64}() else X{64}(n); offset = Z{VL}(m); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let offselt : bits(offs_size) = offset[e*:esize][offs_size-1:0]; let off : integer = if offs_unsigned then UInt(offselt) else SInt(offselt); let addr : bits(64) = base + (off << scale); Hint_Prefetch(addr, pref_hint, level, stream); end; end;


2026-03_rel 2026-03-26 20:48:11

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