Predicate select between predicate register or all-false
This instruction places the contents of the first source predicate register into the destination predicate register if the indexed element of the second source predicate is true, otherwise it sets the destination predicate to all-false. The indexed element is determined by the sum of a general-purpose index register and an immediate, modulo the number of elements. This instruction does not set the condition flags. For programmer convenience, an assembler must also accept predicate-as-counter register names for the destination predicate register and the first source predicate register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | i1 | tszh | 1 | tszl | Rv | 0 | 1 | Pn | 0 | Pm | 0 | Pd | ||||||||||||
| S | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME) && !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); end; let imm5 : bits(5) = i1::tszh::tszl; var esize : integer; var imm : integer; case tszh::tszl of when '0000' => EndOfDecode(Decode_UNDEF); when '1000' => esize = 64; imm = UInt(imm5[4]); when 'x100' => esize = 32; imm = UInt(imm5[4:3]); when 'xx10' => esize = 16; imm = UInt(imm5[4:2]); when 'xxx1' => esize = 8; imm = UInt(imm5[4:1]); end; let n : integer = UInt(Pn); let m : integer = UInt(Pm); let d : integer = UInt(Pd); let v : integer = UInt('011'::Rv);
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pn> |
Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
| <Pm> |
Is the name of the second source scalable predicate register, encoded in the "Pm" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Wv> |
Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field. |
| <imm> |
Is the element index, in the range 0 to one less than the number of vector elements in a 128-bit vector register, encoded in "i1:tszh:tszl". |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let operand1 : bits(PL) = P{}(n); let operand2 : bits(PL) = P{}(m); let idx : bits(32) = X{}(v); let element : integer = (UInt(idx) + imm) MOD elements; var result : bits(PL); if ActivePredicateElement{PL}(operand2, element, esize) then result = operand1; else result = Zeros{PL}; end; P{PL}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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