RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL

Read check write software atomic bit clear on doubleword in memory

This instruction atomically loads a 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the destination register. If the RCW Checks fail or the RCWS Checks fail, the architecture permits writing the value read from the location to memory. If the write is performed, the read and the write occur atomically such that no other modification of the memory location can take place between the read and the write. This instruction updates the condition flags based on the result of the RCW Checks and RCWS Checks.

• If the destination register is not XZR, RCWSCLRA and RCWSCLRAL load from memory with acquire semantics.
• RCWSCLRL and RCWSCLRAL store to memory with release semantics.
• RCWSCLR has neither acquire nor release semantics.

Integer
(FEAT_THE)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_THE) then EndOfDecode(Decode_UNDEF); end; let s : integer{} = UInt(Rs); let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let soft : boolean = TRUE; let acquire : boolean = A == '1' && t != 31; let release : boolean = R == '1'; let tagchecked : boolean = n != 31;