Reverse elements in 64-bit doublewords (vector)
This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||
| U | o0 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let csize : integer{} = 64 >> UInt(o0::U); let esize : integer{} = 8 << UInt(size); if csize <= esize then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let datasize : integer{} = 64 << UInt(Q); let containers : integer = datasize DIV csize;
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = V{}(n); var result : bits(datasize); for c = 0 to containers-1 do let container : bits(csize) = operand[c*:csize]; result[c*:csize] = Reverse{csize}(container, esize); end; V{datasize}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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