REVB, REVH, REVW

Reverse bytes / halfwords / words within elements (predicated)

This instruction reverses the order of 8-bit bytes, 16-bit halfwords or 32-bit words within each active element of the source vector, and places the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.

It has encodings from 6 classes: Byte, merging , Byte, zeroing , Halfword, merging , Halfword, zeroing , Word, merging and Word, zeroing

Byte, merging
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000101size100100100PgZnZd
opcZ

Encoding

REVB <Zd>.<T>, <Pg>/M, <Zn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let swsize : integer = 8; let merging : boolean = TRUE;

Byte, zeroing
(FEAT_SVE2p2 || FEAT_SME2p2)

313029282726252423222120191817161514131211109876543210
00000101size100100101PgZnZd
opcZ

Encoding

REVB <Zd>.<T>, <Pg>/Z, <Zn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let swsize : integer = 8; let merging : boolean = FALSE;

Halfword, merging
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000101size100101100PgZnZd
opcZ

Encoding

REVH <Zd>.<T>, <Pg>/M, <Zn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size IN {'0x'} then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let swsize : integer = 16; let merging : boolean = TRUE;

Halfword, zeroing
(FEAT_SVE2p2 || FEAT_SME2p2)

313029282726252423222120191817161514131211109876543210
00000101size100101101PgZnZd
opcZ

Encoding

REVH <Zd>.<T>, <Pg>/Z, <Zn>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); end; if size IN {'0x'} then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let swsize : integer = 16; let merging : boolean = FALSE;

Word, merging
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000101size100110100PgZnZd
opcZ

Encoding

REVW <Zd>.D, <Pg>/M, <Zn>.D

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; if size != '11' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let swsize : integer = 32; let merging : boolean = TRUE;

Word, zeroing
(FEAT_SVE2p2 || FEAT_SME2p2)

313029282726252423222120191817161514131211109876543210
00000101size100110101PgZnZd
opcZ

Encoding

REVW <Zd>.D, <Pg>/Z, <Zn>.D

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); end; if size != '11' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let g : integer = UInt(Pg); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let swsize : integer = 32; let merging : boolean = FALSE;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D

For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier, encoded in size[0]:

size[0] <T>
0 S
1 D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); let operand : bits(VL) = if AnyActiveElement{PL}(mask, esize) then Z{VL}(n) else Zeros{VL}; var result : bits(VL) = if merging then Z{VL}(d) else Zeros{VL}; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let element : bits(esize) = operand[e*:esize]; result[e*:esize] = Reverse{esize}(element, swsize); end; end; Z{VL}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

The merging variant of this instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and the merging variant of this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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