RSHRNB

Rounding shift right narrow by immediate (bottom)

This instruction shifts each unsigned integer value in the source vector elements right by an immediate value, and places the rounded results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

SVE2
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
010001010tszh1tszlimm3000110ZnZd
opURT

Encoding

RSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let tsize : bits(3) = tszh::tszl; if tsize == '000' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << HighestSetBitNZ(tsize); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let shift : integer = (2 * esize) - UInt(tsize::imm3);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in (tszh :: tszl):

tszh tszl <T>
0 00 RESERVED
0 01 B
0 1x H
1 xx S
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in (tszh :: tszl):

tszh tszl <Tb>
0 00 RESERVED
0 01 H
0 1x S
1 xx D
<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV (2 * esize); let operand : bits(VL) = Z{}(n); var result : bits(VL); for e = 0 to elements-1 do let element : bits(2*esize) = operand[e*:(2*esize)]; let res : integer = (UInt(element) + (1 << (shift-1))) >> shift; result[(2*e + 0)*:esize] = res[esize-1:0]; result[(2*e + 1)*:esize] = Zeros{esize}; end; Z{VL}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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