SADDLP

Signed add long pairwise

This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vector
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q001110size100000001010RnRd
Uop

Encoding

SADDLP <Vd>.<Ta>, <Vn>.<Tb>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if size == '11' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV (2 * esize);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in (size :: Q):

size Q <Ta>
00 0 4H
00 1 8H
01 0 2S
01 1 4S
10 0 1D
10 1 2D
11 x RESERVED
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Tb>

Is an arrangement specifier, encoded in (size :: Q):

size Q <Tb>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 x RESERVED

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = V{}(n); var result : bits(datasize); var sum : bits(2*esize); var op1 : integer; var op2 : integer; for e = 0 to elements-1 do op1 = SInt(operand[(2*e+0)*:esize]); op2 = SInt(operand[(2*e+1)*:esize]); sum = (op1+op2)[2*esize-1:0]; result[e*:(2*esize)] = sum; end; V{datasize}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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