SCVTF (vector, fixed-point)

Signed fixed-point convert to floating-point (vector)

This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
010111110!= 0000immb111001RnRd
Uimmhopcode

Encoding

SCVTF <V><d>, <V><n>, #<fbits>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh IN {'000x'} || (immh IN {'001x'} && !IsFeatureImplemented(FEAT_FP16)) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16; let datasize : integer{} = esize; let elements : integer = 1; let fracbits : integer = (esize * 2) - UInt(immh::immb); let unsigned : boolean = FALSE;

Vector
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q0011110!= 0000immb111001RnRd
Uimmhopcode

Encoding

SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh IN {'000x'} || (immh IN {'001x'} && !IsFeatureImplemented(FEAT_FP16)) then EndOfDecode(Decode_UNDEF); end; if immh[3]::Q == '10' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = if immh IN {'1xxx'} then 64 else if immh IN {'01xx'} then 32 else 16; let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize; let fracbits : integer = (esize * 2) - UInt(immh::immb); let unsigned : boolean = FALSE;

Assembler Symbols

<V>

Is a width specifier, encoded in immh:

immh <V> Architectural Feature
0001 RESERVED -
001x H FEAT_FP16
01xx S -
1xxx D -
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<fbits>

For the "Scalar" variant: is the number of fractional bits, in the range 1 to the operand width, encoded in (immh :: immb):

immh <fbits>
0001 RESERVED
001x 32 - UInt(immh :: immb)
01xx 64 - UInt(immh :: immb)
1xxx 128 - UInt(immh :: immb)

For the "Vector" variant: is the number of fractional bits, in the range 1 to the element width, encoded in (immh :: immb):

immh <fbits>
0001 RESERVED
001x 32 - UInt(immh :: immb)
01xx 64 - UInt(immh :: immb)
1xxx 128 - UInt(immh :: immb)
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in (immh :: Q):

immh Q <T> Architectural Feature
0001 x RESERVED -
001x 0 4H FEAT_FP16
001x 1 8H FEAT_FP16
01xx 0 2S -
01xx 1 4S -
1xxx 0 RESERVED -
1xxx 1 2D -
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = V{}(n); let rounding : FPRounding = FPRoundingMode(FPCR()); let merge : boolean = elements == 1 && IsMerging(FPCR()); var result : bits(128) = if merge then V{128}(d) else Zeros{128}; var element : bits(esize); for e = 0 to elements-1 do element = operand[e*:esize]; result[e*:esize] = FixedToFP{esize, esize}(element, fracbits, unsigned, FPCR(), rounding); end; V{128}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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