Signed fixed-point convert to floating-point (scalar)
This instruction converts the signed value in the 32-bit or 64-bit general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 0 | 0 | 0 | 0 | 1 | 0 | scale | Rn | Rd | ||||||||||||||
| S | rmode | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; if sf == '0' && scale[5] == '0' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let intsize : integer{} = 32 << UInt(sf); let decode_fltsize : integer{} = 8 << UInt(ftype XOR '10'); let fracbits : integer = 64 - UInt(scale); let unsigned : boolean = FALSE;
| <Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Wn> |
Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. |
| <Xn> |
Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
AArch64_CheckFPEnabled(); let merge : boolean = IsMerging(FPCR()); let fltsize : integer{} = if merge then 128 else decode_fltsize; var fltval : bits(fltsize) = if merge then V{fltsize}(d) else Zeros{fltsize}; let intval : bits(intsize) = X{}(n); let rounding : FPRounding = FPRoundingMode(FPCR()); fltval[0+:decode_fltsize] = FixedToFP{decode_fltsize, intsize}(intval, fracbits, unsigned, FPCR(), rounding); V{fltsize}(d) = fltval;
2026-03_rel 2026-03-26 20:48:11
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