SM4 key
This instruction takes an input as a 128-bit vector from the first source SIMD&FP register and a 128-bit constant from the second SIMD&FP register. It derives four iterations of the output key, in accordance with the SM4 standard, returning the 128-bit result to the destination SIMD&FP register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | Rm | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||||||
| O | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SM4) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm);
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
AArch64_CheckFPAdvSIMDEnabled(); let Vm : bits(128) = V{}(m); var intval : bits(32); var const : bits(32); var roundresult : bits(128); roundresult = V{128}(n); for index = 0 to 3 do const = Vm[index*:32]; intval = roundresult[127:96] XOR roundresult[95:64] XOR roundresult[63:32] XOR const; for i = 0 to 3 do intval[i*:8] = Sbox(intval[i*:8]); end; intval = intval XOR ROL(intval, 13) XOR ROL(intval, 23); intval = intval XOR roundresult[31:0]; roundresult[31:0] = roundresult[63:32]; roundresult[63:32] = roundresult[95:64]; roundresult[95:64] = roundresult[127:96]; roundresult[127:96] = intval; end; V{128}(d) = roundresult;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.