Multi-vector signed integer multiply-add long long by vector
This instruction multiplies each signed 8-bit or 16-bit element in the one, two, or four first source vectors by each signed 8-bit or 16-bit element in the second source vector, widens each product to 32 bits or 64 bits, and destructively adds these values to the corresponding 32-bit or 64-bit elements of the ZA quad-vector groups.
The quad-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction is unpredicated.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.
It has encodings from 3 classes: One ZA quad-vector , Two ZA quad-vectors and Four ZA quad-vectors
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | sz | 1 | 0 | Zm | 0 | Rv | 0 | 0 | 1 | Zn | 0 | 0 | 0 | off2 | |||||||||
| U | S | op | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off2::'00'); let nreg : integer{} = 1;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | sz | 1 | 0 | Zm | 0 | Rv | 0 | 0 | 0 | Zn | 0 | 0 | 0 | 0 | o1 | ||||||||
| U | S | op | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let nreg : integer{} = 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | sz | 1 | 1 | Zm | 0 | Rv | 0 | 0 | 0 | Zn | 0 | 0 | 0 | 0 | o1 | ||||||||
| U | S | op | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let nreg : integer{} = 4;
| <T> |
Is the size specifier,
encoded in
|
| <Wv> |
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zm> |
Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. |
| <Zn1> |
Is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn". |
| <Zn2> |
Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" plus 1 modulo 32. |
| <Zn4> |
Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" plus 3 modulo 32. |
CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let vectors : integer = VL DIV 8; let vstride : integer = vectors DIV nreg; let vbase : bits(32) = X{}(v); var vec : integer = (UInt(vbase) + offset) MOD vstride; var result : bits(VL); vec = vec - (vec MOD 4); for r = 0 to nreg-1 do let operand1 : bits(VL) = Z{}((n+r) MOD 32); let operand2 : bits(VL) = Z{}(m); for i = 0 to 3 do let operand3 : bits(VL) = ZAvector{}(vec + i); for e = 0 to elements-1 do let element1 : integer = SInt(operand1[(4 * e + i)*:(esize DIV 4)]); let element2 : integer = SInt(operand2[(4 * e + i)*:(esize DIV 4)]); let product : bits(esize) = (element1 * element2)[esize-1:0]; result[e*:esize] = operand3[e*:esize] + product; end; ZAvector{VL}(vec + i) = result; end; vec = vec + vstride; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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