Signed integer sum of outer products, accumulating
The 8-bit integer variant works with a 32-bit element ZA tile.
The 16-bit integer variant works with a 64-bit element ZA tile.
This instruction multiplies the sub-matrix in the first source vector by the sub-matrix in the second source vector. In case of the 8-bit integer variant, the first source holds SVLS×4 sub-matrix of signed 8-bit integer values, and the second source holds 4×SVLS sub-matrix of signed 8-bit integer values. In case of the 16-bit integer variant, the first source holds SVLD×4 sub-matrix of signed 16-bit integer values, and the second source holds 4×SVLD sub-matrix of signed 16-bit integer values.
Each source vector is independently predicated by a corresponding governing predicate. When an 8-bit source element in case of 8-bit integer variant or a 16-bit source element in case of 16-bit integer variant is Inactive, it is treated as having the value 0.
The resulting SVLS×SVLS widened 32-bit integer or SVLD×SVLD widened 64-bit integer sum of outer products is then destructively added to the 32-bit integer or 64-bit integer destination tile, respectively for 8-bit integer and 16-bit integer instruction variants. This is equivalent to performing a 4-way dot product and accumulate to each of the destination tile elements.
In case of the 8-bit integer variant, each 32-bit container of the first source vector holds 4 consecutive column elements of each row of a SVLS×4 sub-matrix, and each 32-bit container of the second source vector holds 4 consecutive row elements of each column of a 4×SVLS sub-matrix. In case of the 16-bit integer variant, each 64-bit container of the first source vector holds 4 consecutive column elements of each row of a SVLD×4 sub-matrix, and each 64-bit container of the second source vector holds 4 consecutive row elements of each column of a 4×SVLD sub-matrix.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.
It has encodings from 2 classes: 32-bit and 64-bit
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Zm | Pm | Pn | Zn | 0 | 0 | 0 | ZAda | |||||||||||||
| u0 | u1 | S | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let a : integer = UInt(Pn); let b : integer = UInt(Pm); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(ZAda); let op1_unsigned : boolean = FALSE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | Zm | Pm | Pn | Zn | 0 | 0 | ZAda | ||||||||||||||
| u0 | u1 | S | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let a : integer = UInt(Pn); let b : integer = UInt(Pm); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(ZAda); let op1_unsigned : boolean = FALSE; let op2_unsigned : boolean = FALSE;
| <ZAda> |
For the "32-bit" variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field. |
|
For the "64-bit" variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field. |
| <Pn> |
Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field. |
| <Pm> |
Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let dim : integer{} = VL DIV esize; let mask1 : bits(PL) = P{}(a); let mask2 : bits(PL) = P{}(b); let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(dim*dim*esize) = ZAtile{}(da, esize); var result : bits(dim*dim*esize); var prod : integer; for row = 0 to dim-1 do for col = 0 to dim-1 do var sum : bits(esize) = operand3[(row*dim+col)*:esize]; for k = 0 to 3 do if (ActivePredicateElement{PL}(mask1, 4*row + k, esize DIV 4) && ActivePredicateElement{PL}(mask2, 4*col + k, esize DIV 4)) then let op1elt : bits(esize DIV 4) = operand1[(4*row + k)*:(esize DIV 4)]; let op2elt : bits(esize DIV 4) = operand2[(4*col + k)*:(esize DIV 4)]; let element1 : integer = if op1_unsigned then UInt(op1elt) else SInt(op1elt); let element2 : integer = if op2_unsigned then UInt(op2elt) else SInt(op2elt); prod = element1 * element2; sum = sum + prod; end; end; result[(row*dim+col)*:esize] = sum; end; end; ZAtile{dim*dim*esize}(da, esize) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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