SQCVTU (four registers)

Multi-vector signed saturating extract narrow to unsigned integer

This instruction saturates the signed integer value in each element of the four source vectors to unsigned integer value that is quarter the original source element width, and places the results in the quarter-width destination elements.

This instruction is unpredicated.

SME2
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001sz1110011111000Zn00Zd
opNU

Encoding

SQCVTU <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(sz); let n : integer = UInt(Zn::'00'); let d : integer = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in sz:

sz <T>
0 B
1 H
<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Tb>

Is the size specifier, encoded in sz:

sz <Tb>
0 S
1 D
<Zn4>

Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.

Operation

CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV (4 * esize); var result : bits(VL); for r = 0 to 3 do let operand : bits(VL) = Z{}(n+r); for e = 0 to elements-1 do let element : integer = SInt(operand[e*:(4 * esize)]); result[(r*elements + e)*:esize] = UnsignedSat{esize}(element); end; end; Z{VL}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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