Signed saturating doubling multiply-subtract long (by element)
This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.
If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.
The SQDMLSL instruction extracts vector elements from the lower half of the first source register. The SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | size | L | M | Rm | 0 | 1 | 1 | 1 | H | 0 | Rn | Rd | ||||||||||||
| U | o2 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; var Rmhi : bit; case size of when '01' => index = UInt(H::L::M); Rmhi = '0'; when '10' => index = UInt(H::L); Rmhi = M; otherwise => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = esize; let elements : integer = 1; let part : integer = 0;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | 0 | 1 | 1 | 1 | H | 0 | Rn | Rd | ||||||||||||
| U | o2 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; var Rmhi : bit; case size of when '01' => index = UInt(H::L::M); Rmhi = '0'; when '10' => index = UInt(H::L); Rmhi = M; otherwise => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = 64; let part : integer = UInt(Q); let elements : integer = datasize DIV esize;
| <Va> |
Is the destination width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vb> |
Is the source width specifier,
encoded in
|
| <n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Ts> |
Is an element size specifier,
encoded in
|
| <index> |
Is the element index,
encoded in
|
| 2 |
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
encoded in
|
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Ta> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Tb> |
Is an arrangement specifier,
encoded in
|
AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = Vpart{}(n, part); let operand2 : bits(idxdsize) = V{}(m); let operand3 : bits(2*datasize) = V{}(d); var result : bits(2*datasize); var element1 : integer; var element2 : integer; var product : bits(2*esize); var accum : integer; var sat1 : boolean; var sat2 : boolean; element2 = SInt(operand2[index*:esize]); for e = 0 to elements-1 do element1 = SInt(operand1[e*:esize]); (product, sat1) = SignedSatQ{2*esize}(2 * element1 * element2); accum = SInt(operand3[e*:(2*esize)]) - SInt(product); (result[e*:(2*esize)], sat2) = SignedSatQ{2*esize}(accum); if sat1 || sat2 then FPSR().QC = '1'; end; end; V{2*datasize}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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